UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1250
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
27.1 Functions
when oscillation of the main clock is stopped.
means other than reset.
Registers to Check Reset Source.
27.2 Configuration
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any
When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 26.2
The clock monitor automatically stops under the following conditions.
• During oscillation stabilization time after STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit =
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU operates with the internal oscillation clock
The clock monitor includes the following hardware.
0 during main clock operation)
Control register
Internal oscillation
Main clock
Item
clock
Figure 27-1. Timing of Reset via RESET Pin Input
Table 27-1. Configuration of Clock Monitor
CHAPTER 27 CLOCK MONITOR
Clock monitor mode register (CLM)
Clock monitor mode
register (CLM)
Enable/disable
CLME
Configuration
CHAPTER 27 CLOCK MONITOR
Internal reset signal
Page 1250 of 1408
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