UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 393
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 393 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TABnIOC2
TABnIOC0
Remark
• When TABnOLk bit = 0
(c) TABn I/O control register 0 (TABnIOC0)
(d) TABn I/O control register 2 (TABnIOC2)
(e) TABn counter read buffer register (TABnCNT)
TOABnk pin output
The value of the 16-bit counter can be read by reading the TABnCNT register.
Note Clear this bit to 0 when the TOABn0 pin is not used in the PWM output mode.
TABnOL3
n = 0, 1
16-bit counter
0/1
0
TABnOE3 TABnOL2 TABnOE2
0/1
0
Figure 8-26. Setting of Registers in PWM Output Mode (2/3)
0/1
0
0/1
0
TABnOL1
TABnEES1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0/1
0/1
TABnOE1 TABnOL0 TABnOE0
• When TABnOLk bit = 1
TABnEES0 TABnETS1 TABnETS0
0/1
0/1
TOABnk pin output
16-bit counter
0/1
Note
0
0/1
Note
0
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level while
operation of TOABn0 pin is disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Specification of active level of
TOABn1 pin output
0: Active-high
1: Active-low
Specification of active level
of TOABn2 pin output
0: Active-high
1: Active-low
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Specification of active level
of TOABn3 pin output
0: Active-high
1: Active-low
Select valid edge
of external event
count input.
Page 393 of 1408
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