UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 413
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 413 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TABnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTABnCCm signal has been
detected and for calculating an interval.
Remark
INTTABnCC0 signal
TABnCCR0 register
INTTABnCC1 signal
INTTABnCC2 signal
INTTABnCC3 signal
TABnCCR1 register
TABnCCR2 register
TABnCCR3 register
INTTABnOV signal
TIABn0 pin input
TIABn1 pin input
TIABn2 pin input
TIABn3 pin input
n = 0, 1
16-bit counter
TABnOVF bit
TABnCE bit
FFFFH
0000H
Pulse interval
(D
Pulse interval
20
(D
Pulse interval
Pulse interval
0000
0000
0000
0000
+ 1)
00
(D
(D
+ 1)
D
30
10
20
D
+ 1)
+ 1)
00
D
Pulse interval
30
D
(10000H +
D
10
D
01
Pulse interval
Pulse interval
CLR instruction
Cleared to 0 by
(10000H +
Pulse interval
00
(10000H +
− D
D
D
(10000H +
11
21
D
D
00
31
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
D
D
− D
− D
20
)
01
10
D
− D
10
30
20
)
D
)
30
Pulse interval
11
)
D
(10000H +
D
Pulse interval
21
02
(10000H +
D
D
D
− D
12
31
01
− D
Cleared to 0 by
CLR instruction
D
01
Pulse interval
11
)
(10000H +
D
11
D
)
32
12
Pulse interval
D
D
− D
(20000H +
Pulse interval
31
02
D
(D
22
31
Pulse interval
D
D
D
13
)
− D
(10000H +
21
D
12
32
− D
D
03
21
13
D
− D
12
)
CLR instruction
Cleared to 0 by
02
)
Pulse interval
02
(10000H +
D
)
D
33
03
D
Pulse interval
− D
D
22
(D
32
32
23
D
D
)
13
− D
33
D
D
22
D
23
22
03
)
D
33
D
23
Page 413 of 1408
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