UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1085
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
21.2.3 Cautions on data access
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
bit bus. The OHCI area and the PCI bus bridge register area are accessed in 32-bit units, and the USBH converts 16-
bit cycles received from the CPU into 32-bit cycles to start the cycle for the target.
cycle error (INTUSBH1). Accessing misaligned addresses is prohibited since the address is regarded as being
discontinuous. Only accessing 32-bit-aligned continuous addresses is considered to be an access to a continuous
address, and operates normally (see Figure 21-3).
The V850ES/JG3-U and V850ES/JH3-U are connected to the USB host controller via the PCI bus bridge via a 16-
Be sure to access in 32-bit units in accordance with Table 21-2. A data access causing an error results in a PCI
Normal
Normal
Error
Error
Error
Error
Error
Error
Error
Access
Continuous
Continuous
Discontinuous
Discontinuous
Continuous or discontinuous
Continuous or discontinuous
32-bit access
Continuous or discontinuous
Access prohibited area
x x x x 1 C H
x x x x 1 8 H
x x x x 1 4 H
x x x x 1 0 H
x x x x 0 C H
x x x x 0 8 H
x x x x 0 4 H
x x x x 0 0 H
Address
Table 21-2. OHCI and PCI Bus Bridge Register Area (32-bit Access)
1st Cycle
Figure 21-3. Example of Accessing Misaligned Addresses
High Word
1EH
1AH
0EH
0AH
16H
12H
06H
02H
Address
None
Low Word
1CH
0CH
18H
14H
10H
08H
04H
00H
2nd Cycle
[Continous]
The address is continous and is a
32-bit address, so it is
"continous". Whether 00H or
02H comes first does not matter.
[Discontinous]
Even if the address is continuous,
if it is not 32-bit aligned, it is not
considered to be continous.
CHAPTER 21 USB HOST CONTROLLER (USBH)
Write
Read
Write
Read
Write
Read
Write (8 bits)
Write or read
1st Cycle
−
Command
Write
Read
Write
Read
Read
Write
Write (8 bits)
2nd Cycle
Page 1085 of 1408
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