UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1306
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1306 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
32.1.5 Operation
32.1.6 Cautions
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The on-chip debug function is made invalid under the conditions shown in the table below.
When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
(1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN
(2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is
(3) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset is
(4) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.
P56/INTP05/DRST
(program execution), the break function may malfunction.
input from a pin.
generated as soon as the flash memory is rewritten by DMM or read by the RAM monitor function while the user
program is being executed, the CPU and peripheral I/O may not be correctly reset.
OCDM0
RESET
Releasing reset
Remark
DRST Pin
L
H
Figure 32-2. Timing When On-Chip Debug Function Is Not Used
L: Low-level input
H: High-level input
OCDM0 Flag
Low-level input
Invalid
Invalid
0
CHAPTER 32 ON-CHIP DEBUG FUNCTION
Clearing OCDM0 bit
high level can be input/output.
After OCDM0 bit is cleared,
Invalid
Valid
1
Page 1306 of 1408
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