UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 685
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 685 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details,
2. A write operation to bit 0 is ignored.
3. Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while A/D
4. In the following modes, write data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or
5. To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the high-
6. When not using the A/D converter, stop the operation by setting the ADA0CE bit to 0 to
ADA0TMD
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
conversion is enabled (ADA0CE bit = 1).
ADA0PFT registers while A/D conversion is stopped (ADA0CE bit = 0), and then enable
the A/D conversion operation (ADA0CE bit = 1).
•
•
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written in other
modes during A/D conversion (ADA0EF bit = 1), the following will be performed
according to the mode.
•
•
speed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger during
stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0CE bit = 1).
reduce the power consumption.
ADA0EF
Normal conversion mode
One-shot select mode/one-shot scan mode in high-speed conversion mode
In software trigger mode
A/D conversion is stopped and started again from the beginning.
In hardware trigger mode
A/D conversion is stopped, and the trigger standby status is set.
0
1
0
1
Software trigger mode
External trigger mode/timer trigger mode
A/D conversion stopped
A/D conversion in progress
A/D converter status display
Trigger mode specification
CHAPTER 15 A/D CONVERTER
Page 685 of 1408
(2/2)
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