UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1303
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UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) DCK
(3) DMS
(4) DDI
(5) DDO
(6) EV
(7) FLMD0
(8) RESET
This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the
DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling
edge.
This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the
DMS signal.
This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK.
This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal.
This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the signals
output from MINICUBE (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a high-impedance state.
The flash self programming function is used for the function to download data to the flash memory via the
integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a
pull-down resistor to the FLMD0 pin.
The FLMD0 pin can be controlled in either of the following two ways.
<1> To control from MINICUBE
<2> To control from port
This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM0 bit of the OCDM
register set by the user program, on-chip debugging cannot be executed.
MINICUBE, using the RESET pin, to make the DRST pin valid (initialization).
DD
Connect the FLMD0 signal of MINICUBE to the FLMD0 pin.
In the normal mode, nothing is driven by MINICUBE (high impedance).
During a break, MINICUBE raises the FLMD0 pin to the high level when the download function of the
integrated debugger is executed.
Connect any port of the device to the FLMD0 pin.
The same port as the one used by the user program to realize the flash self programming function may be
used.
On the console of the integrated debugger, make a setting to raise the port pin to high level before executing
the download function, or lower the port pin after executing the download function.
For details, refer to the ID850QB Ver. 3.40 Integrated Debugger Operation User's Manual (U18604E).
CHAPTER 32 ON-CHIP DEBUG FUNCTION
Therefore, reset is effected by
Page 1303 of 1408
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