UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 946

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
944
Figure 21-10. Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
There is some delay from the time supply voltage (V
been generated.
In the same way, there is also some delay from the time LVI detection voltage (V
the time LVI reset has been released (see Figure 21-10).
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
<1>:
Operation example 2: When used as interrupt
Supply voltage (V
<Action>
“supply voltage (V
of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of
interrupt request flag register 0L (IF0L) to 0.
action after waiting for the supply voltage fluctuation time.
Confirm that “supply voltage (V
For a system with a long supply voltage fluctuation period near the LVI detection voltage, take the above
LVI reset signal
Minimum pulse width (200
Interrupt requests may be generated frequently.
Take the following action.
words change as follows.
• Supply voltage (V
• Detection voltage (V
LVIF flag
V
DD
LVI
)
DD
) < detection voltage (V
DD
)
LVI
CHAPTER 21 LOW-VOLTAGE DETECTOR
<1>
μ
) → Detection voltage (V
s (MIN.))
→ Input voltage from external input pin (EXLVI)
DD
) ≥ detection voltage (V
User’s Manual U19678EJ1V1UD
LVI
)” when detecting the rising edge of V
DD
) < LVI detection voltage (V
EXLVI
= 1.21 V)
LVI
)” when detecting the falling edge of V
<1>
LVI
LVI
) ≤ supply voltage (V
) until the time LVI reset has
DD
Time
, in the servicing routine
DD
DD
) until
, or