UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 80

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UPD78F1211GB-GAF-AX

Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1211GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
2.3.1 78K0R/IB3
Notes 1. P25/ANI0 to P25/ANI5 are set in the digital input port mode after release of reset.
78
P10/TI02/TO02/TxD0
P11/TI03/TO03/RxD0
P12/TI04/TO04
P13/TI05/TO05
P20/ANI0 to P25/ANI5
P30/SO10/TxD1/TO11
P31/SI10/RxD1/SDA10/
INTP1/TI09
P32/SCK10/SCL10/INTP2
P40/TOOL0
P41/TOOL1
P50/TI06/TO06
P51/TI07/TO07
P80/CMP0P/TMOFF0/
INTP3/PGAI
P81/CMP0M
P83/CMP1M
P120/INTP0/EXLVI
P121/X1/INTP4
P122/X2/EXCLK/INTP5
Table 2-5 shows the types of pin I/O circuits and the recommended connections of unused pins.
2. P80/CMP0P/TMOFF0/INTP3/PGAI, P81/CMP0M and P83/CMP1M are set in the analog input port mode
3. Use recommended connection above in input port mode (see Figure 5-3 Format of Clock Operation
Pin Name
after release of reset.
Mode Control Register (CMC)) when these pins are not used.
Note 2
Note 2
Note 2
Note 3
Note 1
Note 3
8-R
11-G
5-AG
5-AN
8-R
11-J
11-H
8-R
37-C
Table 2-5. Connection of Unused Pins(78K0R/IB3) (1/2)
I/O Circuit Type
CHAPTER 2 PIN FUNCTIONS
User’s Manual U19678EJ1V1UD
I/O
Input
I/O
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
<When N-ch open-drain>
Output
• Set the port output latch to 0: Leave open.
• Set the port output latch to 1: Independently connect to V
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
Independently connect to V
Independently connect to V
Independently connect to AV
Independently connect to V
Independently connect to V
Independently connect to V
Independently connect to AV
Independently connect to V
Recommended Connection of Unused Pins
DD
or V
or V
SS
via a resistor.
DD
DD
SS
DD
DD
DD
REF
REF
via a resistor.
or V
or V
or V
or V
or V
or AV
or AV
SS
SS
SS
SS
SS
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
SS
SS
via a resistor.
via a resistor.
DD

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