UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 361

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Operation
start
During
operation
Operation
stop
TAUS
stop
Remark
Figure 6-70. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of
Set values of the TMRn, TMRp, TMRq registers, TOMn,
TOMp, TOMq, TOLn, TOLp, and TOLq bits cannot be
changed.
Set values of the TDRn, TDRp, and TDRq registers can
be changed after INTTMn of the master channel is
generated.
The TCRn, TCRp, and TCRq registers can always be
read.
The TSRn, TSRp, and TSRq registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
TOEp or TOEq of slave channel is cleared to 0
and value is set to the TOp and TOq bits.
The TAU0EN bit of the PER2 register is cleared to 0.
(Sets the TOEp and TOEq (slave) bits to 1 only when
Sets TOEp and TOEq (slave) bits to 1 (only when
operation is resumed).
The TSn (master), TSp, and TSq (slave) bits of the TS0
register are set to 1 at the same time.
The TTn bit (master), TTp, and TTq (slave) bits are set to
1 at the same time.
To hold the TOp and TOq pin output levels
When holding the TOp and TOq pin output levels is not
necessary
resuming operation.)
The TTn, TTp, and TTq bits automatically return to 0
because they are trigger bits.
n = 00, 02, 04, 06, 08, 10
n < p < q ≤ 11
However, p and q are consecutive integers.
The TSn, TSp, and TSq bits automatically return to 0
because they are trigger bits.
Clears TOp and TOq bits to 0 after
the value to be held is set to the port register.
Switches the port mode register to input mode.
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
PWMs (2/2))
TEn = 1, TEp, TEq = 1
The counter of the master channel loads the TDRn value to
TCRn and counts down. When the count value reaches
TCRn = 0000H, INTTMn is generated. At the same time,
the value of the TDRn register is loaded to TCRn, and the
counter starts counting down again.
At the slave channel 1, the values of TDRp are transferred
to TCRp, triggered by INTTMn of the master channel, and
the counter starts counting down. The output levels of TOp
become active one count clock after generation of the
INTTMn output from the master channel. It becomes
inactive when TCRp = 0000H, and the counting operation
is stopped.
At the slave channel 2, the values of TDRq are transferred
to TCRq, triggered by INTTMn of the master channel, and
the counter starts counting down. The output levels of TOq
become active one count clock after generation of the
INTTMn output from the master channel. It becomes
inactive when TCRq = 0000H, and the counting operation
is stopped. After that, the above operation is repeated.
The TOp and TOq pins output the TOp and TOq set
levels.
The TOp and TOq pin output levels are held by port
function.
The TOp and TOq pin output levels go into Hi-Z output
state.
Power-off status
TEn, TEp, TEq = 0, and count operation stops.
TCRn, TCRp, and TCRq hold count value and stops.
The TOp and TOq output is not initialized but holds
current status.
When the master channel starts counting, INTTMn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOp and TOq bits are cleared to 0 and the TOp
and TOq pins are set to port mode.)
Hardware Status
359