UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 666

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 13-43. Procedure for Resuming Master Transmission/Reception
Changing setting of SPS0 register
Changing setting of SMR0n register
Changing setting of SDR0n register
Changing setting of SCR0n register
Changing setting of SOE0 register
Changing setting of SOE0 register
Starting setting for resumption
Changing setting of SO0 register
Starting communication
Writing to SS0 register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
Set the SOE0n bit to 1 and enable output
from the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SS0n bit of the target channel to 1
and set SE0n bit to 1 (to enable operation).
Set the SOE0n bit to 0 to stop output
from the target channel.
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (f
Re-set the register to change the serial
mode register 0n (SMR0n) setting.
Re-set the register to change the serial
communication operation setting register
0n (SCR0n) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
Set the initial output level of the serial
clock (CKO0n) and serial data (SO0n).
Sets transmit data to the SIOp register (bits
7 to 0 of the SDR0n register) and start
communication.
trigger register 0n (SIR0n).
MCK
)).