UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 745
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UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.7.3 Data reception
After all data are received to the slave, a stop condition is generated and the bus is released.
Note To perform communication via simplified I
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
Simplified I
for the port output mode registers (POM3) (see 4.3 Registers Controlling Port Function for details). When
communicating with an external device with a different potential, set the N-ch open-drain output (V
mode (POM32 = 1) also for the clock input/output pins (SCL10) (see 4.4.4 Connecting to external device
with different potential (2.5 V, 3 V) for details).
2
C
Channel 2 of SAU
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Overrun error detection flag (OVF02) only
8 bits
Max. f
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (ACK transmission)
MSB first
MCK
/4 [Hz] (SDR02[15:9] = 1 or more)
Note
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
2
C, set the N-ch open-drain output (V
f
IIC10
MCK
: Operation clock (f
2
C.
DD
MCK
tolerance) mode (POM31 = 1)
) frequency of target channel
DD
tolerance)
743
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