UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 290

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

288
Address: F01B2H, F01B3H
(6) Timer channel start register 0 (TS0)
Symbol
TS0
TS0 is a trigger register that is used to clear a timer counter (TCRn) and start the counting operation of each
channel.
When a bit (TSn) of this register is set to 1, the corresponding bit (TEn) of timer channel enable status register
0 (TE0) is set to 1. The TSn bit is immediately cleared when operation is enabled (TEn = 1), because it is a
trigger bit.
TS0 can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears TS0 to 0000H.
Caution Be sure to clear bits 15 to 12 to “0”.
Remarks 1. When the TS0 register is read, 0 is always read.
• Interval timer mode
• Event counter mode
• Capture mode
TSn
15
0
1
0
2. n = 00 to 11
Timer operation mode
Table 6-6. Operations from Count Operation Enabled State to TCRn Count Start (1/2)
No trigger operation
TEn is set to 1 and the count operation becomes enabled.
The TCRn count operation start in the count operation enabled state varies depending on each operation
mode (see Table 6-6).
14
0
Figure 6-10. Format of Timer Channel Start Register 0 (TS0)
After reset: 0000H
13
0
12
0
CHAPTER 6 TIMER ARRAY UNIT TAUS
TS11 TS10 TS09 TS08 TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
11
No operation is carried out from start trigger detection (TSn = 1) until count clock
generation.
The first count clock loads the value of TDRn to TCRn and the subsequent count
clock performs count down operation (see 6.3 (6) (a) Start timing in interval
timer mode and up and down count mode).
Writing 1 to TSn bit loads the value of TDRn to TCRn.
The subsequent count clock performs count down operation.
The external trigger detection selected by STSn2 to STSn0 bits in the TMRn
register does not start count operation (see 6.3 (6) (b) Start timing in event
counter mode).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRn and the subsequent count clock
performs count up operation (see 6.3 (6) (c) Start timing in capture mode).
User’s Manual U19678EJ1V1UD
R/W
10
Operation enable (start) trigger of channel n
9
8
Operation when TSn = 1 is set
7
6
5
4
3
2
1
0