UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 633
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(Note and Caution are listed on the next page.)
Address: FFF3CH
ISC4
Other than the above Setting prohibited
0
1
(14) Input switch control register (ISC)
0
0
0
1
Symbol
ISC
ISC1
ISC0
0
1
0
1
ISC3
The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UART0
in coordination with an external interrupt and the timer array unit TAUS.
When bit 0 is set to 1, the input signal of the serial data input (R
(INTP0) that can be used to detect a wakeup signal.
When bit 1 is set to 1, the input signal of the serial data input (R
wake up signal can be detected, the low width of the sync break field, and the pulse width of the sync field can
be measured by the timer.
The ISC2 to ISC4 bits are set to select the P52/SLTI/SLTO pin as the timer I/O pin of timer channels 0, 1, and
8 to 11 (This bits are not provided in the 78K0R/IB3).
ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ISC register to 00H.
0
0
0
1
1
0
ISC2
Uses the input signal of the TI07 pin as a timer input (normal operation).
Input signal of R
break field and the pulse width of the sync field).
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
Uses the input signal of the R
0
1
1
0
1
0
7
0
After reset: 00H
Input
P00/
P52/
SLTI
P00/
P00/
P00/
P00/
TI00
TI00
TI00
TI00
TI00
pin
Channel 0
Figure 13-17. Format of Input Switch Control Register (ISC)
Output
TO00
SLTO
TO00
TO00
TO00
TO00
X
P01/
P52/
P01/
P01/
P01/
P01/
D0 pin is used as timer input (detects the wakeup signal and measures the low width of the sync
pin
6
0
R/W
Input
SLTI
P52/
pin
Channel 1
−
−
−
−
−
CHAPTER 13 SERIAL ARRAY UNIT
X
D0 pin as an external interrupt (detects the wakeup signal).
Switching channel 7 input of timer array unit TAUS
5
0
User’s Manual U19678EJ1V1UD
Output
SLTO
P52
pin
Switching external interrupt (INTP0) input
Selecting P52/SLTI/SLTO Pin as Timer I/O Pin
−
−
−
−
−
Input
P16/
P16/
P52/
SLTI
P16/
P16/
P16/
TI08
TI08
TI08
TI08
TI08
pin
Channel 8
ISC4
4
Output
SLTO
TO08
TO08
TO08
TO08
TO08
P16/
P16/
P52/
P16/
P16/
P16/
pin
TI09
TI09
TI09
TI09
TI09
ISC3
Input
P31/
P31/
P31/
P52/
SLTI
P31/
P31/
3
pin
Channel 9
X
X
Note 2
Note 2
Note 2
Note 2
Note 2
D0) pin is selected as a timer input, so that
D0) pin is selected as an external interrupt
Output
TO09
TO09
TO09
SLTO
TO09
TO09
P17/
P17/
P17/
P52/
P17/
P17/
pin
ISC2
2
Input
SLTI
P74/
TI10
P74/
TI10
P74/
TI10
P74/
TI10
P52/
P74/
TI10
Channel 10
pin
Output
SLTO
TO10
TO10
TO10
TO10
TO10
P73/
P73/
P73/
P73/
P52/
P73/
ISC1
pin
1
Input
P75/
P75/
P75/
P75/
P75/
P52/
SLTI
TI11
TI11
TI11
TI11
TI11
Channel 11
pin
ISC0
Output
0
TO11
TO11
TO11
TO11
TO11
SLTO
P30/
P30/
P30/
P30/
P30/
P52/
pin
631
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