UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 619

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03)
(4) Serial communication operation setting register 0n (SCR0n)
SMR0n
Symbol
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark
SCR0n register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity
bit, start bit, stop bit, and data length.
Rewriting SCR0n register is prohibited when the register is in operation (when SE0n = 1).
SCR0n register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets SCR0n register to 0087H.
For successive transmission, the next transmit data is written by setting MD0n0 bit to 1 when SDR0n data has run
out.
CKS
SIS
0n0
0n2
0n0
MD
MD
15
0n
0
1
0
1
0
0
1
1
n: Channel number (n = 0 to 3)
Falling edge is detected as the start bit.
The input communication data is captured as is.
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
Transfer end interrupt
Buffer empty interrupt
(Occurs when data is transferred from the SDR0n register to the shift register.)
CCS
0n1
MD
14
0n
0
1
0
1
Figure 13-6. Format of Serial Mode Register 0n (SMR0n) (2/2)
CSI mode
UART mode
Simplified I
Setting prohibited
13
0
12
0
2
C mode
Controls inversion of level of receive data of channel n in UART mode
CHAPTER 13 SERIAL ARRAY UNIT
11
0
User’s Manual U19678EJ1V1UD
10
0
Selection of interrupt source of channel n
Setting of operation mode of channel n
9
0
STS
0n
8
After reset: 0020H
7
0
SIS
0n0
6
5
1
R/W
4
0
3
0
0n2
MD
2
0n1
MD
1
0n0
MD
617
0