UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 319

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7 Operation of Timer Array Unit TAUS as Independent Channel
6.7.1 Operation as interval timer/square wave output
(1) Interval timer
(2) Operation as square wave output
The timer array unit can be used as a reference timer that generates INTTMn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
In products other than the 78K0R/IB3, in addition to CK00 to CK03, the subsystem clock divided by 4 (f
can also be selected as the count clock. Consequently, the interval timer can be operated with the count clock
fixed to f
change the clock selected as f
all channels of timer array unit TAUS (timer channel stop register 0 (TT0) = 0FFFH).
TOn performs a toggle operation at the same time INTTMn is generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOn can be calculated by the following
expressions.
TCRn operates as a down counter in the interval timer mode.
The TCRn register loads the value of TDRn register at the first count clock after the channel start trigger bit
(TSn) of timer channel start register 0 (TS0) is set to 1. If MDn0 of TMRn = 0 at this time, INTTMn is not output
and TOn is not toggled. If MDn0 of TMRn = 1, INTTMn is output and TOn is toggled.
After that, TCRn count down in synchronization with the count clock.
When TCRn = 0000H, INTTMn is output and TOn is toggled at the next count clock. At the same time, TCRn
loads the value of TDRn again. After that, the same operation is repeated.
TDRn can be rewritten at any time. The new value of TDRn becomes valid from the next period.
Remarks 1. n = 0 to 11 (n = 02 to 07 and 11 in for timer output pin (TOn) of 78K0R/IB3)
Generation period of INTTMn (timer interrupt) = Period of count clock × (Set value of TDRn + 1)
• Period of square wave output from TOn = Period of count clock × (Set value of TDRn + 1) × 2
• Frequency of square wave output from TOn = Frequency of count clock/{(Set value of TDRn + 1) × 2}
SUB
2. f
/4, regardless of the f
f
CLK
SUB
: CPU/peripheral hardware clock frequency
: Subsystem clock oscillation frequency
CLK
CHAPTER 6 TIMER ARRAY UNIT TAUS
CLK
(change the value of the system clock control register (CKC)) after stopping
frequency (main system clock, subsystem clock). However, be sure to
User’s Manual U19678EJ1V1UD
SUB
317
/4)