UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 701

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6 Operation of UART (UART0, UART1) Communication
reception (R
parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and
the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to
transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus
can be implemented by using timer array unit TAUS with an external interrupt (INTP0).
This is a start-stop synchronization function using two lines: serial data transmission (T
[Data transmission/reception]
[Interrupt function]
[Error detection flag]
The LIN-bus is supported in UART0 (0, 1 channels of unit)
[LIN-bus functions]
UART0 uses channels 0 and 1 of SAU.
UART1 uses channels 2 and 3 of SAU.
Note
Caution When using serial array unit as UARTs, the channels of both the transmitting side (even-number
UART performs the following four types of communication operations.
• UART transmission
• UART reception
• LIN transmission (UART0 only) (See 13.6.3.)
• LIN reception (UART0 only)
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
• Framing error, parity error, or overrun error
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
0
1
2
3
Channel
X
D) lines. By using these two communication lines, each data frame, which consist of a start bit, data,
CSI00 and CSI01 are only available in the 44-pin and 48-pin products of the 78K0R/IC3 and in the
78K0R/ID3 and 78K0R/IE3.
channel) and the receiving side (odd-number channel) can be used only as UARTs.
Used as CSI
CSI00
CSI01
CSI10
−
Note
Note
(See 13.6.1.)
(See 13.6.2.)
(See 13.6.4.)
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
UART0 (supporting LIN-bus)
Used as UART
UART1
Used as Simplified I
IIC10
−
−
−
X
D) and serial data
2
C
699