UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 108

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) CALLT instruction table area
(3) Option byte area
(4) On-chip debug security ID setting area
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The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT).
Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2
bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to
010C3H when the boot swap is used. For details, see CHAPTER 23 OPTION BYTE.
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID
setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not
used and at 000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see
CHAPTER 25 ON-CHIP DEBUG FUNCTION.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U19678EJ1V1UD