UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 768

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3 Registers Controlling Serial Interface IICA
766
Address: F00F0H
Serial interface IICA is controlled by the following eight registers.
(1) Peripheral enable register 0 (PER0)
Symbol
PER0
• Peripheral enable register 0 (PER0)
• IICA control register 0 (IICCTL0)
• IICA flag register (IICF)
• IICA status register (IICS)
• IICA control register 1 (IICCTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port mode register 6 (PM6)
• Port register 6 (P6)
PER0 is used to enable or disable supplying the clock to the peripheral hardware macro. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICAEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PER0 to 00H.
Cautions 1. When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0, writing to
Notes
RTCEN
IICAEN
2. Be sure to clear bits 0, 1, 3, and 6 (78K0R/IB3: Bits 0, 1, 3, 4, 6, 38-pin and 44-pin of
<7>
0
1
After reset: 00H
a control register of serial interface IICA is ignored, and, even if the register is read, only
the default value is read (except for port mode register 6 (PM6), port register 6 (P6)).
78K0R/IC3) of the PER0 register to 0.
Note 1
1. RTCEN bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 of PER0 register is
2. IICAEN bit is not provided in the 78K0R/IB3 and the 38-pin and 44-pin products of the
fixed to 0.
78K0R/IC3. In the 78K0R/IB3 and the 38-pin and 44-pin products of the 78K0R/IC3, bit 4
of PER0 register is fixed to 0.
Stops input clock supply.
• SFR used by serial interface IICA cannot be written.
• Serial interface IICA is in the reset status.
Enables input clock supply.
• SFR used by serial interface IICA can be read/written.
Figure 14-5. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
CHAPTER 14 SERIAL INTERFACE IICA
ADCEN
<5>
User’s Manual U19678EJ1V1UD
Control of serial interface IICA input clock
IICAEN
<4>
Note 2
3
0
SAU0EN
<2>
1
0
0
0