UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 155

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UPD78F1211GB-GAF-AX

Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1211GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.2.1 Port 0
mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 0 (PU0).
P00/TI00
P01/TO00
Port 0 is I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
This port can also be used for timer I/O.
Reset signal generation sets port 0 to input mode.
Figures 4-1 and 4-2 shows block diagrams of port 0.
Cautions 1.
P0:
PU0:
PM0:
RD:
WRxx:
Remark With products not provided with an EV
2.
WR
WR
WR
RD
PORT
Read signal
Write signal
To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0)
and bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
To use the crest interrupt signal (INTTMM0) and valley interrupt signal (INTTMV0) of the
inverter control function, output from timer channel 0 must be enabled (by setting TOE00 to
1).
Therefore, P01/TO00 cannot be used as a general-purpose output port.
Port register 0
Pull-up resistor option register 0
Port mode register 0
PU
PM
V
SS
78K0R/IB3
.
Output latch
Alternate
function
PM00
PU00
(P00)
PU0
PM0
P0
(38-pin)
Figure 4-1. Block Diagram of P00
CHAPTER 4 PORT FUNCTIONS
User’s Manual U19678EJ1V1UD
78K0R/IC3
(44-pin)
DD
or EV
SS
pin, replace EV
(48-pin)
DD
78K0R/ID3
with V
EV
DD
DD
P-ch
, or replace EV
P00/TI00
78K0R/IE3
SS
153
with

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