UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 511
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UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(a) Timer mode register q (TMRq) of slave channels 3, 5, 7 (real-time output channel (TRCq = 0))
(b) Other registers of slave channels 3, 5, 7 (real-time output channel (TRCq = 0))
TMRq
Remark
CKSq
TRO0:TROq
TOE0:TOEq
TO0:TOq
TOM0:TOMq
TOT0:TOTq
TOL0:TOLq
TDE0:TDEq
TRE0:TREq
TRC0:TRCq
TME0:TMEq
15
0
When Complementary Modulation Output Function (Slave Channels 3, 5, 7) Is Used
Operation clock selection
14
0: Selects CK00 as operation clock of channel q.
0
q = 03, 05, 07
CCS1q
13
1
CCS0q
1: Enables the TOq output operation by counting operation.
1: Outputs a high level from TOq.
1: Inverted output (active-low)
1: Enables dead time control.
1: Enables real-time output.
0: Outputs a low level as real-time output.
1: Outputs a high level as real-time output.
0: Stops modulated output.
1: Enables modulated output.
0: Stops the TOq output operation by counting operation.
0: Outputs a low level from TOq.
1: Sets slave channel output mode.
1: Sets triangular wave PWM output.
0: Positive logic output (active-high)
0: Does not operate as the real-time output trigger generation channel.
Figure 7-98. Example of Set Contents of Registers
12
0
CHAPTER 7 INVERTER CONTROL FUNCTIONS
Count clock selection
TERq
MAS
10B: Selects count clock of master channel.
11
0
Slave/master selection
STSq2
0: slave channel
10
1
User’s Manual U19678EJ1V1UD
STSq1
9
1
Start trigger selection
STSq0
110B: Selects trigger of dead time control trigger generation
0
8
CISq1
channel.
0
7
CISq0
0
6
Selection of TIq pin input edge
00B: Sets 00B because these are not used.
Operation mode of channel q
1000B: One-count mode
5
0
MDq4
4
1
Start trigger during operation
MDq3
1: Trigger input is valid.
3
0
MDq2
0
2
MDq1
1
0
MDq0
0
1
509
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