UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 253

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6 Controlling Clock
5.6.1 Example of setting internal high-speed oscillator
oscillation clock. Use the system clock control register (CKC) to specify the division ratio for the clock to be supplied
to the CPU/peripheral hardware after releasing reset. When using the default division setting (f
register is not required to be set.
5.6.2 Example of setting 40 MHz internal high-speed oscillator
oscillation clock. To subsequently using 40 MHz internal high-speed oscillation clock, set the operation speed mode
control register (OSMC) and then the 40 MHz internal high-speed oscillation control register (DSCCTL).
After a reset release, the CPU/peripheral hardware clock (f
[Register settings]
<1> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
After a reset release, the CPU/peripheral hardware clock (f
[Register settings] Set the register in the order of <1> to <8> below.
<1> Set the OSMC register so that the microcontroller operates at a frequency exceeding 10 MHz.
<2> Set (1) the FSEL bit and then wait for 10
<3> Set (1) the DSCON bit of the DSCCTL register to operate the 40 MHz internal high-speed oscillator.
<4> Set (1) the DSCON bit and then wait for 100
<5> Set the DSPO bit of the DSCCTL register to 1, supply f
<6> Set (1) the SELDSC bit of the DSCCTL register to switch the internal high-speed oscillation clock from 8 MHz
Note
DSCCTL
DSCCTL
DSCCTL
clock.
OSMC
control block, and supply f
to 40 MHz.
CKC
CLS bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 is fixed to 0.
CLS
7
0
7
0
7
0
7
0
7
0
Note
CSS
CLK
6
0
6
0
6
0
6
0
6
0
/2 to the CPU and other peripheral hardware.
CHAPTER 5 CLOCK GENERATOR
MCS
User’s Manual U19678EJ1V1UD
0
0
0
0
0
5
5
5
5
5
μ
s.
μ
s.
MCM0
4
0
4
0
4
0
4
0
4
0
CLK
CLK
CLK
) always starts operating with the internal high-speed
) always starts operating with the internal high-speed
(40 MHz) to the timer array unit TAUS and inverter
DSCS
DSCS
DSCS
3
1
3
0
3
0
3
0
3
0
SELDSC
SELDSC
SELDSC
MDIV2
0/1
2
2
0
2
0
2
0
2
1
MDIV1
DSPO
DSPO
DSPO
0/1
1
1
0
1
0
1
1
1
1
IH
/2 = 4 MHz), the CKC
DSCON
DSCON
DSCON
MDIV0
FSEL
0/1
0
0
1
0
1
0
1
0
1
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