UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 754

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.7.6 Procedure for processing errors that occurred during simplified I
Figures 13-105 and 13-106.
752
Reads serial data register 02
(SDR02).
Reads serial status register 02 (SSR02).
Writes serial flag clear trigger register 02
(SIR02).
Sets ST02 bit of the serial channel stop
register 0 (ST0) to 1.
Creates stop condition.
Creates start condition.
Sets SS02 bit of the serial channel start
register 0 (SS0) to 1.
Reads serial data register 02
(SDR02).
Reads serial status register 02
(SSR02).
Writes serial flag clear trigger register
02 (SIR02) to 1.
The procedure for processing errors that occurred during simplified I
Figure 13-106. Processing Procedure in Case of Parity Error (ACK error) in Simplified I
Software Manipulation
Software Manipulation
Figure 13-105. Processing Procedure in Case of Parity Error or Overrun Error
CHAPTER 13 SERIAL ARRAY UNIT
The BFF02 bit of the SSR02 register is
set to 0 and channel 2 is enabled to
receive data.
Error flag is cleared.
The BFF02 bit of the SSR02 register is
set to 0 and channel 2 is enabled to
receive data.
Error flag is cleared.
The SE02 bit of the serial channel enable
status register 0 (SE0) is set to 0 and
channel 2 stops operation.
The SE02 bit of the serial channel enable
status register 0 (SE0) is set to 1 and
channel 2 is enabled to operate.
User’s Manual U19678EJ1V1UD
Hardware Status
Hardware Status
2
C (IIC10) communication is described in
2
C (IIC10) communication
This is to prevent an overrun error if
the next reception is completed
during error processing.
Error type is identified and the read
value is used to clear error flag.
Only error generated at the point of
reading can be cleared, by writing
the value read from the SSR02
register to the SIR02 register without
modification.
This is to prevent an overrun error if the
next reception is completed during
error processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSR02 register to the SIR02
register without modification.
Slave is not ready for reception
because ACK is not returned.
Therefore, a stop condition is created,
the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
transmission can be redone from
address transmission.
Remark
Remark
2
C Mode