UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 863
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UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.5.4 Holding DMA transfer pending by DWAITn
the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set
system, a DMA transfer can be held pending by setting DWAITn to 1.
width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by
setting DWAITn to 1.
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of
To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock
After setting DWAITn to 1, it takes two clocks until a DMA transfer is held pending.
Caution When DMA transfer is held pending while using both DMA channels, be sure to held the
Remarks 1. n: DMA channel number (n = 0, 1)
Figure 16-10. Example of Setting for Holding DMA Transfer Pending by DWAITn
2. 1 clock: 1/f
DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If the DMA
transfer of one channel is executed while that of the other channel is held pending, DMA
transfer might not be held pending for the latter channel.
CLK
(f
CLK
: CPU clock)
CHAPTER 16 DMA CONTROLLER
User’s Manual U19678EJ1V1UD
Starting DMA transfer
Wait for 2 clocks
Wait for 9 clocks
Main program
DWAITn = 1
DWAITn = 0
P10 = 1
P10 = 0
861
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