UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 285

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
(3) Timer mode register n (TMRn)
Symbol
TMRn
TMRn sets an operation mode of channel n. It is used to select an operation clock (f
whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the
timer input, and an operation mode (interval, capture, event counter, one-count, capture & one-count, or up
and down count
Rewriting TMRn is prohibited when the register is in operation (when TE0 = 1). However, bits 7 and 6 (CISn1,
CISn0) can be rewritten even while the register is operating with some functions (when TE0 = 1) (for details,
see 6.7 Independent Channel Operation Function of Timer Array Unit TAUS and 6.8 Simultaneous
Channel Operation Function of Timer Array Unit TAUS).
TMRn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears TMRn to 0000H.
Note These modes are used with the inverter control function. For the inverter control function, refer to
Note These settings are used with the inverter control function. For the inverter control function, refer to
Caution Be sure to clear bits 14 and 5 to “0”.
Remark
F01C8H, F01C9H (TMR08) to F01CEH, F01CFH (TMR11)
Operation clock (f
depending on the setting of the CCS1n and CCS0n bits.
Count clock (f
CKS
CCS
CHAPTER 7 INVERTER CONTROL FUNCTIONS.
CKS
CHAPTER 7 INVERTER CONTROL FUNCTIONS.
1n
15
n
0
1
0
0
1
1
n
n = 00 to 11 (Timer input pin (TIn) of 78K0R/IB3: n = 02 to 07 and 09).
Operation clock CK00 set by timer clock select register 0 (TPS0) : timer channels 0 to 7
Operation clock CK02 set by timer clock select register 0 (TPS0) : timer channels 8 to 11
Operation clock CK01 set by timer clock select register 0 (TPS0) : timer channels 0 to 7
Operation clock CK03 set by timer clock select register 0 (TPS0) : timer channels 8 to 11
CCS
0n
14
0
1
0
1
0
Note
).
TCLK
Operation clock (f
Valid edge of input signal input from TIn pin/subsystem clock divided by 4 (f
Selects master channel count clock (when the channel is used as a slave channel with the
simultaneous channel operation functions)
Selects master channel interrupt signal (when the channel is used as a slave channel with the
simultaneous channel operation functions)
CCS
Figure 6-7. Format of Timer Mode Register n (TMRn) (1/3)
13
1n
MCK
) is used for the timer/counter, output controller, and interrupt controller.
) is used by the edge detector. A sampling clock and a count clock (f
CCS
12
0n
CHAPTER 6 TIMER ARRAY UNIT TAUS
MAST
ERn
11
MCK
User’s Manual U19678EJ1V1UD
) specified by CKSn bit
STS
Selection of operation clock (f
10
n2
Selection of count clock (f
STS
n1
9
STS
n0
8
After reset: 0000H
Note
Note
.
.
CIS
n1
7
CIS
MCK
n0
6
TCLK
) of channel n
) of channel n
5
0
R/W
MD
n4
4
MD
n3
TCLK
SUB
3
/4)
MCK
) are generated
MD
n2
), a count clock,
2
MD
n1
1
MD
n0
283
0