UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 923

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.1 Register for Confirming Reset Source
store which source has generated the reset request.
Many internal reset generation sources exist in the 78K0R/Ix3. The reset control flag register (RESF) is used to
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF clear TRAP, WDRF, INIRF and LVIRF.
Notes 1.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 19-3.
Flag
TRAP bit
WDRF bit
INIRF bit
LVIRF bit
Address: FFFA8H
Symbol
RESF
Reset Source
2.
The value after reset varies depending on the reset source.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-
chipdebug emulator.
WDRF
LVIRF
TRAP
TRAP
INIRF
7
0
1
0
1
0
1
0
1
Cleared (0)
After reset: 00H
RESET Input
Table 19-3. RESF Status When Reset Request Is Generated
Figure 19-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
6
0
Note 1
Cleared (0)
Reset by POC
CHAPTER 19 RESET FUNCTION
R
Internal reset request by execution of illegal instruction
User’s Manual U19678EJ1V1UD
5
0
Internal reset request by a reset processing check error
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
Set (1)
Held
Held
Held
Execution of
WDRF
Instruction
Reset by
Illegal
4
Held
Set (1)
Held
Held
Reset by WDT
3
0
2
0
Reset by INIRF
Held
Held
Set (1)
Held
INIRF
Note 2
1
Held
Held
Held
Set (1)
Reset by LVI
LVIRF
0
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