UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 778

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

776
(5) IICA control register 1 (IICCTL1)
Address: F0231H
IICCTL1
Symbol
This register is used to set the operation mode of I
IICCTL1 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD and DAD bits are
read-only.
Set the IICCTL1 register, except the WUP bit, while operation of I
register 0 (IICCTL0) is 0).
Reset signal generation clears this register to 00H.
Notes 1.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) WUP
(see Figure 14-22 Flow When Setting WUP = 1).
Clear (0) WUP after the address has matched or an extension code has been received. The subsequent
communication can be entered by clearing (0) WUP. (The wait must be released and transmit data must be
written after WUP has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE bit is set to 1.
Condition for clearing (WUP = 0)
• Cleared by instruction (after address match or
extension code reception)
WUP
WUP
7
0
1
SDA0
SCL0
2.
After reset: 00H
Figure 14-9. Format of IICA Control Register 1 (IICCTL1) (1/2)
Bits 4 and 5 are read-only.
The status of IIC status register (IICS) must be checked and WUP must be set during the
period shown below.
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
6
0
Check the IICS operation status and set
WUP during this period.
CHAPTER 14 SERIAL INTERFACE IICA
CLD
<5>
R/W
User’s Manual U19678EJ1V1UD
<1>
Note 1
DAD
<4>
The maximum time from reading IICS to setting
WUP is the period from <1> to <2>.
A6
2
Control of address match wakeup
C and detect the statuses of the SCL0 and SDA0 pins.
A5
SMC
<3>
Condition for setting (WUP = 1)
• Set by instruction (when MSTS, EXC, and COI are
A4
“0”, and STD also “0” (communication not
entered))
DFC
A3
2
<2>
C is disabled (bit 7 (IICE) of IICA control
Note 2
A2
1
0
A1
A0
<2>
0
0
R/W