UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 132
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1211GB-GAF-AX
Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Address
F01CAH
F01CBH
F01CCH
F01CDH
F01CEH
F01CFH
F01EAH Timer real-time output enable
F01ECH Timer real-time output register 0
F01EEH Timer real-time control register 0
F01C6H
F01C7H
F01C8H
F01C9H
F01D0H
F01D1H
F01D2H
F01D3H
F01D4H
F01D5H
F01D6H
F01D7H
F01E8H Timer triangle wave output mode
F01F0H Timer modulation output enable
F01F2H Timer dead-time output enable
F0220H
F0222H
F0224H
F0226H
F0228H
130
Timer counter register 11
Timer mode register 08
Timer mode register 09
Timer mode register 10
Timer mode register 11
Timer status register 08
Timer status register 09
Timer status register 10
Timer status register 11
register 0
register 0
register 0
register 0
TAU option mode register
TAU option status register
TAU option Hi-Z start trigger
register
TAU option Hi-Z stop trigger
register
TAU option control register
Special Function Register (SFR)
Name
Table 3-6. Extended SFR (2nd SFR) List (5/6)
TCR11
TMR08
TMR09
TMR10
TMR11
TSR08
TSR09
TSR10
TSR11
TOT0
TRE0
TRO0
TRC0
TME0
TDE0
OPMR
OPSR
OPHS
OPHT
OPCR
CHAPTER 3 CPU ARCHITECTURE
Symbol
User’s Manual U19678EJ1V1UD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
16-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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√
√
√
√
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Reset
After
√
√
√
√
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