UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 798

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UPD78F1211GB-GAF-AX

Manufacturer Part Number
UPD78F1211GB-GAF-AX
Description
MCU 16BIT 78K0R/LX3 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1211GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
UPD78F1211GB-GAF-AX
Manufacturer:
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Quantity:
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796
14.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register (IICF) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT) of IICCTL0 is set to 1 while the bus is not used (after a stop condition is detected), a start
condition is automatically generated and wait state is set.
If an address is written to the IICA shift register (IICA) after bit 4 (SPIE) of IICCTL0 was set to 1, and it was
detected by generation of an interrupt request signal (INTIICA) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IICA before the
stop condition is detected is invalid.
When STT has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS (bit 7 of the IICA status register
(IICS)) after STT is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
released by setting bit 6 (LREL) of IICA control register 0 (IICCTL0) to 1 and saving communication).
Remark IICWL: IICA low-level width setting register
Wait time from setting STT = 1 to checking the MSTS flag:
(IICWL setting value + IICWH setting value + 4) + t
IICWH: IICA high-level width setting register
t
f
F
CLK
:
:
SDA0 and SCL0 signal falling times
CPU/peripheral hardware clock frequency
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
F
× 2 × f
CLK
[clocks]

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