UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 438

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

436
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAUS
stop
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMRn and TMRm registers of two channels to
be used (determines operation mode of channels).
An interval (period) value is set to the TDRn register of
the master channel, and the number of interrupts to be
thinned is set to the TDRm register of the slave channel.
Sets the TOEn bit (master channel) to 1 (only when
operation is resumed).
The set values of the TDRn and TDRm registers can be
changed.
The TCRn and TCRm registers can always be read.
The TTn (master) and TTm (slave) bits are set to 1 at
the same time.
The TAU0EN and TAUOPEN bits of the PER2
register are cleared to 0.
Determines clock frequencies of CK00 and CK01.
Sets the TSn (master) and TSm (slave) bits to 1 at the
same time.
The TSn and TSm bits automatically return to 0
because they are trigger bits.
The TTn and TTm bits automatically return to 0
because they are trigger bits.
Figure 7-49. Operation Procedure When Interrupt Signal Thinning Function Is Used
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEn = 1, TEm = 1
The counter (TCRn) of the master channel counts down.
When the count value reaches TCRn = 0000H, the value of
TDRn is loaded to TCRn again and the count operation is
continued. By detecting TCRn = 0000H, INTTMn is
generated and TOn performs toggle operation.
The counter (TCRm) of the slave channel counts down every
time an INTTMn signal of the master channel is detected.
When the count value reaches TCRm = 0000H, the value of
TDRm is loaded to TCRm again and the count operation is
continued. By detecting TCRm = 0000H, INTTMm is
generated.
TEn and TEm = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
At the master channel, TCRn loads the value of TDRn by
count clock input. INTTMn is generated and TOn is
toggled when the MDn0 bit of the TMRn register is 1.
At the slave channel, TCRm loads the value of TDRm and
enters a state to wait for detection of INTTMn of the
master channel.
TCRn and TCRm hold count values and stop.
All circuits are initialized and SFR of each channel is also
initialized.
(The TOn and TOm bits are cleared to 0 and the TOn and
TOm pins are set to port mode.)
Hardware Status