UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 959
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
Note A flowchart is shown on the next page.
2. Remark m = 0, 1, n = 0 to 7
words change as follows.
• Supply voltage (V
• Detection voltage (V
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
No
Figure 23-11. Example of Software Processing After Reset Release (1/2)
Restarting timer array unit
(TTmn = 1 → TSmn = 1)
Setting timer array unit
(to measure 50 ms)
50 ms has passed?
voltage or higher
processing <1>
processing <2>
(TMIFmn = 1?)
Clearing WDT
Initialization
Initialization
(LVIF = 0?)
Setting LVI
Detection
Reset
No
Yes
LVI reset
DD
)
LVI
) → Detection voltage (V
→ Input voltage from the external input pin (EXLVI)
Yes
;
; Setting of detection level by LVIS.
; f
; Initial setting for port.
; The timer counter is cleared and the timer is started.
Check the reset source, etc.
The low-voltage detector operates (LVION = 1).
CLK
Source: f
Timer starts (TSmn = 1).
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
= Internal high-speed oscillation clock (8.16 MHz (MAX.)/2) (default)
where comparison value = 796: ≅ 50 ms
MCK
(8.16 MHz (MAX.)/2)/2
mn = 00 to 07, 10 to 13
EXLVI
CHAPTER 23 LOW-VOLTAGE DETECTOR
Note
= 1.21 V)
8
,
959
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