UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 879
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(Caution is listed on the next page.)
Notes 1. That bit is not provided in the 40-pin and 44-pin products of the 78K0R/KC3-L.
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, and IF2L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When
the IF0L and IF0H, and IF1L and IF1H registers are combined to form 16-bit registers IF0 and IF1, they can be set by
a 16-bit memory manipulation instruction. Using the IF2L register as the IF2 register can be set also by using a 16-bit
memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFE0H After reset: 00H R/W
Address: FFFE1H
Address: FFFE2H
Address: FFFE3H
Address: FFFD0H
Symbol
Symbol
Symbol
Symbol
Symbol
2. Those bits are not provided in the 40-pin product of the 78K0R/KC3-L.
IF0H
IF1H
IF0L
IF1L
IF2L
Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L) (1/2)
increases by 2 clocks.
SREIF0
TMIF03
TMIF04
PIF5
<7>
<7>
<7>
<7>
7
0
After reset: 00H
After reset: 00H
After reset: 00H
After reset: 00H
CSIIF01
TMIF02
SRIF0
MDIF
PIF4
<6>
<6>
<6>
<6>
6
0
R/W
R/W
R/W
R/W
CSIIF00
TMIF01
STIF0
PIF3
<5>
<5>
<5>
5
0
5
0
PIF7
DMAIF1
TMIF00
PIF2
<4>
<4>
<4>
<4>
4
0
Note 2
IICAIF
DMAIF0
KRIF
PIF1
PIF6
<3>
<3>
<3>
<3>
<3>
CHAPTER 18 INTERRUPT FUNCTIONS
Note 1
RTCIIF
CMPIF1
SREIF1
TMIF07
PIF0
<2>
<2>
<2>
<2>
<2>
Note 2
RTCIF
CMPIF0
TMIF06
SRIF1
LVIIF
<1>
<1>
<1>
<1>
<1>
Note 2
CSIIF10
WDTIIF
TMIF05
IICIF10
STIF1
ADIF
<0>
<0>
<0>
<0>
0
0
879
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