UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 744
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
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Note 1
SE
01
0
1
78K0R/Kx3-L
Notes 1. Serial channel enable status register 0 (SE0) is a read-only status register which is set using serial channel
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark X: Don’t care
MD
012
0
0
0
0
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
2. When channel 1 is set to UART0 reception, this pin becomes an RxD0 function pin. In this case, set channel 0
3. This pin can be set as a port function pin.
5. When using UART0 transmission and reception in a pair, set channel 0 to UART0 transmission (refer to Table
6. Serial mode register 00 (SMR00) of channel 0 must also be set during UART0 reception. For details, refer to
MD0
Table 14-6. Relationship Between Register Settings and Pins (Channel 1: CSI01, UART0 Reception)
11
0
1
0
1
to operation stop mode or UART0 transmission (refer to Table 14-5).
When channel 0 is set to CSI00, this pin cannot be used as an RxD0 function pin. In this case, set channel 1 to
operation stop mode or CSI01.
14.6.2 (1) Register setting.
statrt register 0 (SS0) and serial channel stop register 0 (ST0).
m (SOm).
14-5).
SOE
01
0
0
1
1
0
1
1
0
Note 4
Note 4
Note 4
Note 4
SO
0/1
0/1
0/1
0/1
01
1
1
1
1
CKO
Note 4
Note 4
Note 4
0/1
0/1
0/1
01
1
1
1
1
1
TXE
01
0
0
1
1
0
1
1
0
RXE
01
0
1
0
1
1
0
1
1
Note 3
Note 3
PM
72
×
1
1
1
0
0
0
×
P72 PM
Note 3
Note 3
×
×
×
×
1
1
1
×
Note 3
Note 3
Note 3
Note 3
71
×
1
×
1
1
×
1
×
P71 PM
Note 3
Note 3
Note 3
Note 3
×
×
×
×
×
×
×
×
Note 3
Note 3
Note 3
Note 3
70
×
×
0
0
×
0
0
×
P70 PM
Note 3
Note 3
Note 3
Note 3
×
×
1
1
×
1
1
×
Note 2
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
74
×
×
×
×
×
×
×
1
P74
Note 2
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
×
×
×
×
×
×
×
×
CHAPTER 14 SERIAL ARRAY UNIT
stop mode
transmission
transmission
transmission
transmission
Operation
Operation
/reception
/reception
reception
reception
reception
Notes 5, 6
UART0
Master
Master
Master
CSI01
CSI01
CSI01
CSI01
CSI01
CSI01
mode
Slave
Slave
Slave
(output)
(output)
(output)
SCK01/
SCK01
SCK01
SCK01
SCK01
SCK01
SCK01
INTP6/
INTP6/
INTP6/
(input)
(input)
(input)
KR2/
KR2/
KR2/
P72
P72
P72
INTP5/
INTP5/
INTP5/
INTP5/
INTP5/
SI01/
KR1/
KR1/
KR1/
KR1/
KR1/
SI01
SI01
SI01
SI01
P71
P71
P71
P71
P71
Pin Function
INTP4/
INTP4/
INTP4/
INTP4/
INTP4/
SO01/
SO01
SO01
SO01
SO01
KR0/
KR0/
KR0/
KR0/
KR0/
P70
P70
P70
P70
P70
SI00/RxD0/
SI00/KR4/
SI00/KR4/
SI00/KR4/
SI00/KR4/
SI00/KR4/
SI00/KR4/
KR4/P74
KR4/P74
RxD0
Note 2
P74
P74
P74
P74
P74
P74
744
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