UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 832
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(4) Data ~ restart condition ~ address
(communication status)
(communication status)
Notes 1. Make sure that the time between the rise of the SCL0 pin signal and the generation of the start
(8 or 9 clock wait)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
(SP detection)
(ST detection)
(ACK control)
(ACK control)
Master side
(SP trigger)
SDA0 (bus)
(ST trigger)
SCL0 (bus)
(clock line)
(data line)
Slave side
(interrupt)
(interrupt)
MSTS
Bus line
WTIM
INTIICA
WTIM
INTIICA
MSTS
WREL
WREL
ACKD
ACKE
ACKD
ACKE
TRC
SPD
TRC
IICA
STT
SPT
IICA
STD
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
condition after a restart condition has been issued is at least 4.7
at least 0.6
H
H
H
L
L
H
L
H
H
L
L
D
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
1
3
Figure 15-32. Example of Master to Slave Communication
μ
s when specifying fast mode.
D
1
2
D
1
1
D
1
0
<7>
ACK
<8>
<i>
Note 2
<ii>
Note 1
<iii>
CHAPTER 15 SERIAL INTERFACE IICA
AD6
μ
s when specifying standard mode and
Restart condition
AD5
Slave address
AD4
AD3
AD2
AD1
832
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