UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 115
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
3.2.17 RESET
3.2.18 REGC
to V
3.2.19 FLMD0
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to EV
When the external reset pin is used, design the circuit based on V
This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
This is a pin for setting flash memory programming mode.
Perform either of the following processing.
SS
(a) In normal operation mode
(b) In self programming mode
(c) In flash memory programming mode
via a capacitor (0.47 to 1
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the V
externally because it is internally pulled down by reset. However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see
26.5 (1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the V
It is recommended to leave this pin open when using the self programming function. To pull it down externally,
use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer.
This supplies a writing voltage of the V
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull
it down externally, use a resistor of 1 kΩ to 200 kΩ.
μ
F: target).
SS
pin.
DD
level to the FLMD0 pin.
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
SS
level before reset release but does not have to be pulled down
REGC
V
SS
DD
.
DD0
or EV
DD1
.
115
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