UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 15
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 756
CHAPTER 16 MULTIPLIER/DIVIDER ................................................................................................... 840
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
15.1 Functions of Serial Interface IICA........................................................................................... 756
15.2 Configuration of Serial Interface IICA .................................................................................... 759
15.3 Registers Controlling Serial Interface IICA............................................................................ 762
15.4 I
15.5 I
15.6 Timing Charts ........................................................................................................................... 825
16.1 Functions of Multiplier/Divider................................................................................................ 840
16.2 Configuration of Multiplier/Divider ......................................................................................... 840
16.3 Register Controlling Multiplier/Divider................................................................................... 845
16.4 Operations of Multiplier/Divider.............................................................................................. 846
2
2
14.9.2 78K0R/KF3-L, 78K0R/KG3-L ....................................................................................................... 747
15.4.1 Pin configuration........................................................................................................................... 776
15.4.2 Setting transfer clock by using IICWL and IICWH registers.......................................................... 777
15.5.1 Start conditions............................................................................................................................. 778
15.5.2 Addresses .................................................................................................................................... 779
15.5.3 Transfer direction specification..................................................................................................... 779
15.5.4 Acknowledge (ACK) ..................................................................................................................... 780
15.5.5 Stop condition............................................................................................................................... 781
15.5.6 Wait .............................................................................................................................................. 782
15.5.7 Canceling wait .............................................................................................................................. 784
15.5.8 Interrupt request (INTIICA) generation timing and wait control..................................................... 785
15.5.9 Address match detection method ................................................................................................. 786
15.5.10 Error detection............................................................................................................................ 786
15.5.11 Extension code........................................................................................................................... 786
15.5.12 Arbitration ................................................................................................................................... 787
15.5.13 Wakeup function......................................................................................................................... 789
15.5.14 Communication reservation........................................................................................................ 792
15.5.15 Cautions ..................................................................................................................................... 796
15.5.16 Communication operations......................................................................................................... 797
15.5.17 Timing of I
16.4.1 Multiplication operation................................................................................................................. 846
16.4.2 Division operation......................................................................................................................... 847
C Bus Mode Functions........................................................................................................... 776
C Bus Definitions and Control Methods .............................................................................. 778
2
C interrupt request (INTIICA) occurrence ................................................................. 804
15
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