UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 540
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
11.2 Configuration of Clock Output/Buzzer Output Controller
11.3 Registers Controlling Clock Output/Buzzer Output Controller
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The clock output/buzzer output controller includes the following hardware.
Note The port mode register and port register to be set differ depending on the product.
Remark n = 0:
The following two registers are used to control the clock output/buzzer output controller.
• Clock output select registers n (CKSn)
• Port mode registers 5, 14 (PM5, PM14)
Note The port register to be set differ depending on the product.
(1) Clock output select registers n (CKSn)
Remark n = 0:
These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and
set the output clock.
Select the clock to be output from the PCLBUZn pin by using the CKSn register.
The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
78K0R/KC3-L (48-pin), 78K0R/KD3-L: P14
78K0R/KE3-L, 78K0R/KG3-L:
78K0R/KF3-L:
78K0R/KC3-L (48-pin), 78K0R/KD3-L: None
78K0R/KE3-L, 78K0R/KG3-L:
78K0R/KF3-L:
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
Control registers
78K0R/KC3-L (48-pin), 78K0R/KD3-L
78K0R/KC3-L (48-pin), 78K0R/KD3-L
Table 11-1. Configuration of Clock Output/Buzzer Output Controller
Item
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Clock output select registers n (CKSn)
Port mode registers 5, 14 (PM5, PM14)
Port registers 5, 14 (P5, P14)
Note
PM14, P14
PM5, P5, PM14, P14
PM14
PM5, PM14
Configuration
Note
Note
540
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