UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 1120
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
31.6.2 Serial interface IICA
(T
Notes 1.
31.6.3 On-chip debug (UART)
(T
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
SCL0 clock frequency
Setup time of restart condition
Hold time
Hold time when SCL0 = “L”
Hold time when SCL0 = “H”
Data setup time (reception)
Data hold time (transmission)
Setup time of stop condition
Bus-free time
Transfer rate
TOOL1 output frequency
A
A
SDA0
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
SCL0
= −40 to +85°C, 1.8 V ≤ V
= −40 to +85°C, 1.8 V ≤ V
2.
Stop
condition
Parameter
Parameter
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of t
(acknowledge) timing.
t
LOW
Start
condition
t
Note 2
HD:STA
Note 1
t
LOW
DD
DD
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)
f
= EV
= EV
TOOL1
Symbol
t
f
t
t
t
t
t
t
t
t
HD:DAT
SCL
SU:STA
HD:STA
LOW
HIGH
SU:DAT
HD:DAT
SU:STO
BUF
Symbol
DD0
DD0
= EV
= EV
Flash memory programming mode
2.7 V ≤ V
1.8 V ≤ V
High speed mode: f
Normal mode: f
DD1
DD1
HD:DAT
IICA serial transfer timing
≤ 5.5 V, V
≤ 5.5 V, V
t
HIGH
DD
DD
t
SU:DAT
is during normal transfer and a wait state is inserted in the ACK
Conditions
≤ 5.5 V
< 2.7 V
Conditions
CLK
SS
SS
CLK
≥ 1 MHz
= EV
= EV
≥ 3.5 MHz
t
SU:STA
SS0
SS0
= EV
= EV
Restart
condition
SS1
SS1
Standard Mode
MIN.
250
f
4.7
4.0
4.7
4.0
4.0
4.7
CLK
MIN.
0
0
= AV
= AV
/2
t
12
HD:STA
SS
SS
MAX.
3.45
= 0 V)
= 0 V)
100
TYP.
High-Speed Mode
MIN.
100
0.6
0.6
1.3
0.6
0.6
1.3
0
0
MAX.
f
3.33
CLK
2.5
10
/6
t
SU:STO
MAX.
400
0.9
Mbps
MHz
MHz
Stop
condition
Unit
bps
Unit
kHz
μ
μ
μ
μ
ns
μ
μ
μ
s
s
s
s
s
s
s
1120
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