UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 766
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. Bit 1 (STT) becomes 0 when it is read after data setting.
Note The signal of this bit is invalid while IICE0 is 0.
Cautions concerning set timing
• For master reception:
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
• Cannot be set to 1 at the same time as stop condition trigger (SPT).
• Setting the STT bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT = 0)
• Cleared by setting the STT bit to 1 while communication
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
device
STT
reservation is prohibited.
0
1
Note
2. IICRSV: Bit 0 of IIC flag register (IICF)
Do not generate a start condition.
When bus is released (in standby state, when IICBSY = 0):
When a third party is communicating:
In the wait state (when master device):
If this bit is set (1), a start condition is generated (startup as the master).
Generates a restart condition after releasing the wait.
• When communication reservation function is enabled (IICRSV = 0)
• When communication reservation function is disabled (IICRSV = 1)
STCF:
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (3/4)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
Even if this bit is set (1), the STT bit is cleared and the STT clear flag (STCF) is set (1). No start
condition is generated.
Bit 7 of IIC flag register (IICF)
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKE bit has been cleared to 0 and slave has been notified of final reception.
during the wait period that follows output of the ninth clock.
Start condition trigger
Condition for setting (STT = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
766
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