UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 103
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
3.2.5 P40 to P47 (port 4)
clock I/O, data I/O for a flash memory programmer/debugger, clock output, and timer I/O.
Notes 1. INTP1 and TI05/TO05 are shared with P50 and P05, respectively, in the 78K0R/KF3-L.
(1) Port mode
(2) Control mode
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P40/TOOL0
P41/TOOL1
P42/TI04/TO04
P43/SCK01
P44/SI01
P45/SO01
P46/INTP1/TI05/TO05
P47/INTP2
P40 to P47 function as an I/O port. These pins also function as external interrupt request input, serial interface data I/O,
The following operation modes can be specified in 1-bit units.
(b) TI03
(c) TO03
(d) RTC1HZ
P40 to P47 function as an I/O port. P40 to P47 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte).
P40 to P47 function as serial interface data I/O, clock I/O, external interrupt request input, data I/O for a flash memory
programmer/debugger, clock output, and timer I/O.
2. INTP2 is shared with P51, in the 78K0R/KF3-L.
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03.
This is a timer output pin from 16-bit timer 03.
This is a real-time counter correction clock (1 Hz) output pin.
(
μ
PD78F10xx: xx = 10, 11, 12,
78K0R/KF3-L
P46
P47
27, 28)
√
√
√
√
√
√
Note 1
Note 2
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
(
μ
PD78F10xx: xx = 13, 14,
78K0R/KG3-L
29, 30)
√
√
√
√
√
√
√
√
103
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