UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 687
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
14.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40,
communication is described in Figure 14-74.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40, CSI41)
Reads serial data register mn (SDRmn).
Reads serial status register mn
(SSRmn).
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Remark
CSI41) communication
Software Manipulation
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
78K0R/KG3-L (
Figure 14-74. Processing Procedure in Case of Overrun Error
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
The BFFmn bit of the SSRmn register is
set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
Hardware Status
mn = 00 to 02
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
CHAPTER 14 SERIAL ARRAY UNIT
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Remark
687
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