UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 777
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
15.4.2 Setting transfer clock by using IICWL and IICWH registers
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Setting transfer clock on master side
(2) Setting IICWL and IICWH registers on slave side
Caution Note the minimum f
Remarks 1. Calculate the rise time (t
At this time, the optimal setting values of the IICWL and IICWH registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
• When the normal mode
(The fractional parts of all setting values are truncated.)
• When the fast mode
• When the normal mode
Transfer clock =
IICWL =
IICWH = (
IICWL =
IICWH = (
IICWL = 1.3
IICWH = (1.2
IICWL = 4.7
IICWH = (5.3
operation frequency for serial interface IICA is determined according to the mode.
2. IICWL: IICA low-level width setting register
Normal mode:
Fast mode:
differ depending on the pull-up resistance and wire load.
IICWH: IICA high-level width setting register
t
t
f
F
R
CLK
:
:
Transfer clock
Transfer clock
Transfer clock
Transfer clock
:
μ
μ
IICWL + IICWH + f
μ
μ
s × f
s × f
0.52
0.47
s − t
s − t
0.48
0.53
SDA0 and SCL0 signal falling times
SDA0 and SCL0 signal rising times
CPU/peripheral hardware clock frequency
CLK
CLK
R
R
− t
− t
f
f
F
F
CLK
CLK
) × f
) × f
CLK
× f
× f
f
− t
− t
CLK
CLK
CLK
= 3.5 MHz (MIN.)
= 1 MHz (MIN.)
CLK
CLK
R
R
operation frequency when setting the transfer clock. The minimum f
− t
− t
CLK
R
F
F
) and fall time (t
) × f
) × f
(t
R
CLK
CLK
+ t
F
)
F
) of the SDA0 and SCL0 signals separately, because they
CHAPTER 15 SERIAL INTERFACE IICA
777
CLK
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