UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 401
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) Timer data register mn (TDRmn)
Remark
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0
bits of timer mode register mn (TMRmn).
The value of the TDRmn register can be changed at any time.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
(ii) When timer data register mn (TDRmn) is used as capture register
(i) When timer data register mn (TDRmn) is used as compare register
Address: FFF18H, FFF19H (TDR00), FFF1AH, FFF1BH (TDR01),
TDRmn
Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an
interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten.
Caution The TDRmn register does not perform a capture operation even if a capture trigger is input,
The count value of timer/counter register mn (TCRmn) is captured to the TDRmn register when the capture
trigger is input.
A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode
register mn (TMRmn).
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KF3-L, 78K0R/KG3-L:
FFF64H, FFF65H (TDR02) to FFF6EH, FFF6FH (TDR07)
FFF70H, FFF71H (TDR10) to FFF76H, FFF77H (TDR13)
15
when it is set to the compare function.
14
13
Figure 8-7. Format of Timer Data Register mn (TDRmn)
FFF19H (TDR00)
12
11
mn = 00 to 07, 10 to 13
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
10
9
8
7
After reset: 0000H
6
5
CHAPTER 8 TIMER ARRAY UNIT
FFF18H (TDR00)
4
R/W
3
2
1
0
401
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