UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 1012
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
8-bit
operation
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
Mnemonic
SUBC
AND
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
Except r = A
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
Operands
Note 3
Note 3
Bytes
Table 29-5. Operation List (8/17)
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
Note 1 Note 2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Clocks
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
r, CY ← r − A − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A, CY ← A − (HL + B) − CY
A, CY ← A − (HL + C) − CY
A, CY ← A − (ES:addr16) − CY
A, CY ← A − (ES:HL) − CY
A, CY ← A − ((ES:HL) + byte) − CY
A, CY ← A − ((ES:HL) + B) − CY
A, CY ← A − ((ES:HL) + C) − CY
A ← A ∧ byte
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
r ← r ∧ A
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A ← A ∧ (HL + byte)
A ← A ∧ (HL + B)
A ← A ∧ (HL + C)
A ← A ∧ (ES:addr16)
A ← A ∧ (ES:HL)
A ← A ∧ ((ES:HL) + byte)
A ← A ∧ ((ES:HL) + B)
A ← A ∧ ((ES:HL) + C)
CPU
) selected by the system clock control
Operation
CHAPTER 29 INSTRUCTION SET
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
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1012
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