UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 432
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0R/Kx3-L
8.4 Basic Rules of Simultaneous Channel Operation Function
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
channels forming one simultaneous channel operation function).
channel operation function in 8.4 Basic Rules of Simultaneous Channel Operation Function do not apply to the
channel groups.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as
(9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels
(11) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave
If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous
Remark
Example: If channel 2 of the TAU0 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5,
be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of
master channel. The CKS bit (bit 15 of timer mode register mn (TMRmn)) of the slave channel that operates in
combination with the master channel must be the same value as that of the master channel.
a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels
with lower channel numbers.
master channel as a source clock.
in combination must be set at the same time.
combination must be set at the same time.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
etc.) can be set as a slave channel.
If channel 0 of the TAU1 is set as a master channel, channel 1 or those that follow (channels 1, 2, 3)
can be set as a slave channel.
master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
mn = 00 to 07, 10 to 13
CHAPTER 8 TIMER ARRAY UNIT
432
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