UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 360
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 360 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
6. The HALT mode current when STOP mode and when the subsystem clock is used
7. If the FLPC bit is set to a frequency of 1 MHz or less and then set (1), it cannot be
can be reduced by setting the RTCLPC bit to 1. However, no clock can be supplied
to the peripheral functions other than the real-time counter during HALT mode while
subsystem clock is selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable
registers 0 (PER0), to 1, and all of bits 0 to 6 of the PER0 register, bits 0 to 7 of
peripheral enable register 1 (PER1), and bits 0 to 7 of peripheral enable register 2
(PER2) to 0 before setting subsystem clock HALT mode.
cleared (0) or set to a frequency of more than 1 MHz.
CHAPTER 7 CLOCK GENERATOR
360
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