UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 451
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 451 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
Remark
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
TAU
stop
78K0R/KF3-L, 78K0R/KG3-L:
To hold the TOmn pin output level
When holding the TOmn pin output level is not necessary
The TAU0EN and TAU1EN bits of the PER0 and PER2
registers are cleared to 0.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn changes as
below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Clears the TOmn bit to 0 after the value to
be held is set to the port register.
Switches the port mode register to input mode.
Figure 8-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)
Software Operation
Note
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
The TOmn pin output level is held by port function.
The TOmn pin output level goes into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOmn bit is cleared to 0 and the TOmn pin is set to
port mode.)
CHAPTER 8 TIMER ARRAY UNIT
Hardware Status
451
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