UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 733
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
14.8.3 Data reception
After all data are received to the slave, a stop condition is generated and the bus is released.
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
Simplified I
2. • 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
• 78K0R/KF3-L, 78K0R/KG3-L
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
To perform communication via simplified I
1) for the port output mode registers (POM3) (see 5.3 Registers Controlling Port Function for details).
When communicating with an external device with a different potential, set the N-ch open-drain output (V
tolerance) mode (POM32 = 1) also for the clock input/output pins (SCL10) (see 5.4.4 Connecting to
external device with different potential (2.5 V, 3 V) for details).
To perform communication via simplified I
POM143 = 1) for the port output mode registers (POM0, POM14) (see 6.3 Registers Controlling Port
Function for details). When communicating with an external device with a different potential, set the N-ch
open-drain output (V
SCL20) (see 6.4.4 Connecting to external device with different potential (2.5 V, 3 V) for details).
2
C
8 bits
Max. f
Channel 2 of SAU0
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Overrun error detection flag (OVFmn) only
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (ACK transmission)
MSB first
MCK
/4 [Hz] (SDRmn[15:9] = 1 or more)
DD
tolerance) mode (POM04, POM142 = 1) also for the clock input/output pins (SCL10,
Note 2
IIC10
2
2
C, set the N-ch open-drain output (V
C, set the N-ch open-drain output (V
mn = 02
mn = 02, 10
f
MCK
: Operation clock frequency of target channel
Channel 0 of SAU1
SCL20, SDA20
INTIIC20
CHAPTER 14 SERIAL ARRAY UNIT
2
C.
Note 2
IIC20
DD
DD
tolerance) mode (POM31 =
tolerance) mode (POM03,
Note 1
733
DD
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