UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 22
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
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1.1 Features
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
78K0R/Kx3-L
RENESAS MCU
Notes1. Those are not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
Notes 1. This is 11 KB when the self-programming function is used.
• 20 MHz Internal high-speed oscillation clock: 20 MHz (TYP.)
• 8 MHz Internal high-speed oscillation clock: 8 MHz (TYP.)
• 1 MHz Internal high-speed oscillation clock: 1 MHz (TYP.)
• 16-bit timer:
• Watchdog timer:
• Real-time counter: 1 channel
Minimum instruction execution time can be changed from high speed (0.05
system clock) to ultra low-speed (61
General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
ROM, RAM capacities
On-chip internal high-speed oscillation clocks
On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
Self-programming (with boot swap function/flash shield window function)
On-chip debug function
On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
On-chip watchdog timer (operable with the dedicated internal low-speed oscillation clock)
On-chip multiplier/divider (16 bits × 16 bits, 32 bits ÷ 32 bits)
On-chip key interrupt function
On-chip clock output/buzzer output controller
On-chip BCD adjustment
I/O ports: 33 to 89 (N-ch open drain: 2/4
Timer: 10/14 channels
Flash ROM
256 KB
192 KB
128 KB
96 KB
64 KB
48 KB
32 KB
16 KB
2. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
2. This is 7 KB when the self-programming function is used.
3. This is 2 KB when the self-programming function is used.
12 KB
8 KB
3 KB
1.5 KB
10 KB
RAM
6 KB
4 KB
2 KB
1 KB
Note 3
Note 2
Note 1
8/12 channels
1 channel
40 pins
μ
PD78F1000
78K0R/KC3-L
μ
μ
μ
PD78F1003
PD78F1002
PD78F1001
Note 2
44 pins
μ
−
−
−
−
−
s: @ 32.768 kHz operation with subsystem clock)
Note 1
CHAPTER 1 OUTLINE
)
48 pins
Note 1
−
78K0R/KD3-L
μ
μ
μ
PD78F1006
PD78F1005
PD78F1004
52 pins
−
−
−
−
−
−
78K0R/KE3-L 78K0R/KF3-L 78K0R/KG3-L
μ
μ
μ
PD78F1009
PD78F1008
PD78F1007
64 pins
−
−
−
−
−
−
μ
s: @ 20 MHz operation with high-speed
μ
μ
μ
μ
μ
PD78F1028
PD78F1027
PD78F1012
PD78F1011
PD78F1010
80 pins
−
−
−
−
R01UH0106EJ0300
μ
μ
μ
μ
PD78F1030
PD78F1029
PD78F1014
PD78F1013
100 pins
−
−
−
−
−
Oct 01, 2010
Rev.3.00
22
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