UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 659
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Register setting
Notes 1. Those bits are invalid while operating serial allay unit 1.
SMRmn
SCRmn
SDRmn
SOm
(a) Serial mode register mn (SMRmn)
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
(Remark is listed on the next page.)
(b) Serial communication operation setting register mn (SCRmn)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
2. Those bits are invalid while operating serial allay unit 2.
Figure 14-52. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
CKSmn
TXEmn
Selection of the data and clock
phase (For details about the
setting, see 14.3 Registers
Controlling Serial Array Unit.)
0/1
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
15
15
15
15
1
0
RXEmn
CCSmn
14
0
14
14
14
1
0
DAPmn
0/1
13
13
13
13
0
0
Baud rate setting
MCK
CKPmn
0000000
0/1
12
) of channel n
12
12
12
0
0
(CSI00, CSI01, CSI10, CSI20, CSI40, CSI41) (1/2)
11
0
11
11
11
0
1
EOCmn
CKOm2
×
10
Notes 1, 2
10
10
0
10
0
PTCmn1
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
CKOm1
×
9
0
0
Note 1
9
9
9
PTCmn0
STSmn
CKOm0
0
8
8
0
×
8
0
8
DIRmn
0/1
7
0
0
7
7
7
SISmn0
0
6
0
6
6
0
6
SLCmn1
5
0
5
5
0
1
5
CHAPTER 14 SERIAL ARRAY UNIT
Transmit data setting
SLCmn0
SIOp
0
4
0
0
4
4
4
Interrupt source of channel n
0
0
3
1: Buffer empty interrupt
3
3
1
0: Transfer end interrupt
3
Setting of data length
0/1
MDmn2
DLSmn2
SOm2
0: 7-bit data length
1: 8-bit data length
2
1
2
0
2
2
Note 2
DLSmn1
0/1
MDmn1
SOm1
1
1
0
1
1
1
Note 1
DLSmn0
MDmn0
SOm0
0/1
0/1
0/1
0
0
0
0
659
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